Giorgos Dimitrakopoulos – Publications

Book

G. Dimitrakopoulos, A. Psarras, I. Seitanidis “Microarchitecture of Network-on-Chip Routers”, Springer, ISBN 978-1-4614-4300-1, Oct. 2014. web

Book chapters

  1. G. Dimitrakopoulos and D. Bertozzi, “Switch architecture”, Chapter 2 in “Designing Network-on-Chip Architectures in the Nanoscale Era”, J. Flich and D. Bertozzi (editors), Dec. 2010, CRC press, ISBN: 978-1-4398-3710-8

  2. G. Dimitrakopoulos, “Logic Design of Basic Switch Components”, Chapter 3 in “Designing Network-on-Chip Architectures in the Nanoscale Era”, J. Flich and D. Bertozzi (editors), Dec. 2010, CRC press, ISBN: 978-1-4398-3710-8

  3. G. Dimitrakopoulos, C. Kachris, E. Kalligeros, “Switch design for soft interconnection networks”, in “Embedded Systems Design with FPGAs”, P. Athanas, D. Pnevmatikatos, N. Sklavos (editors), Springer.

Journals

  1. A. Psarras, S. Moisidis, C. Nicopoulos, G. Dimitrakopoulos, "Networks-on-Chip with Double-Data-Rate Links" , to appear in IEEE Transactions on Circuits and Systems I, 2017. paper

  2. A. Psarras, M. Paschou, C. Nicopoulos, G. Dimitrakopoulos, "A Dual-Clock Multiple-Queue Shared Buffer", in IEEE Transactions on Computers, vol. 66, no. 10, pp. 1809 - 1815, Oct. 2017. paper

  3. E. Karampasis, N. Papanikolaou, D. Voglitsis, M. Loupis, A. Psarras, A. Boubaris, D. Baros, G. Dimitrakopoulos, "Active Thermoelectric Cooling Solutions for Airspace Applications: the THERMICOOL Project", in IEEE Access, 2017. paper

  4. A. Psarras, I. Seitanidis, C. Nicopoulos, G. Dimitrakopoulos "ShortPath: A Network-on-Chip Router with Fine-Grained Pipeline Bypassing", in IEEE Transactions on Computers, vol. 65, no. 10, pp. 3136-3147, Oct. 2016. paper

  5. K. Chrysanthou, P. Englezakis, A. Prodromou, A. Panteli, C. Nicopoulos ,Y. Sazeides, G. Dimitrakopoulos, "An On-Line and Real-Time Fault Detection and Localization Mechanism for Network-on-Chip Architectures" , in ACM Transactions on Architecture and Code optimisation (TACO), Vol. 13, No. 2, June 2016. paper

  6. A. Psarras, J. Lee, I. Seitanidis, C. Nicopoulos, G. Dimitrakopoulos "PhaseNoC: Versatile Network Traffic Isolation through TDM-Scheduled Virtual Channels", in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.35, no.5, pp.844-857, May 2016. paper

  7. I. Seitanidis, A. Psarras, K. Chrysanthou, C. Nicopoulos, G. Dimitrakopoulos "ElastiStore: Flexible Elastic Buffering for Virtual-Channel-based Networks-on-Chip", in IEEE Transactions on VLSI Systems, vol.23, no.12, pp.3015-3028, Dec. 2015. paper

  8. D. Bertozzi, G. Dimitrakopoulos, J. Flich, S. Sonntag, "The fast evolving landscape of on-chip communication", in Design Automation of Embedded Systems, Springer, vol. 19, no. 1-2, March 2015, pp. 59-76. paper

  9. G. Dimitrakopoulos, E. Kalligeros, K. Galanopoulos “Merged Switch Allocation and Traversal in Network-On-Chip Switches”, in IEEE Transactions on Computers, Oct. 2013, pp. 2001-2012. paper

  10. D. S. Gracia, G. Dimitrakopoulos, T. Monreal Arnal, M. G.H. Katevenis, and V. Vinals Yufera “LP-NUCA: Networks-in-Cache for high-performance low-power embedded processors”, in IEEE Transactions on VLSI Systems. vol.20, no.8, pp. 1510-1523, Aug. 2012. paper

  11. H. T. Vergos, G. Dimitrakopoulos “On modulo 2n+1 adder design”, in IEEE Transactions on Computers, vol.61, no.2, pp. 173-186, Feb. 2012. paper

  12. N. Chrysos, G. Dimitrakopoulos “Practical High-Throughput Crossbar Scheduling”, in IEEE Micro, Micro's Top Picks from Hot Interconnects 16, Summer 2009. paper

  13. G. Dimitrakopoulos, K. Galanopoulos, C. Mavrokefalidis, D. Nikolos, “Low-Power Leading Zero Counting and Anticipation Logic for High-Speed Floating Point Units”, in IEEE Transactions on VLSI Systems, July 2008. paper

  14. G. Dimitrakopoulos, C. Mavrokefalidis, K. Galanopoulos, and D. Nikolos, “Sorter Based Permutation Units for Media-Enhanced Microprocessors”, in IEEE Transactions on VLSI Systems, vol. 15, no. 6, June 2007. paper

  15. C. Efstathiou, H. T. Vergos, G. Dimitrakopoulos, and D. Nikolos, “Efficient Diminished-1 Modulo 2n+1 Multipliers”, in IEEE Transactions on Computers, vol. 54, no. 4, April 2005. paper

  16. G. Dimitrakopoulos and D. Nikolos, “High-Speed Parallel-Prefix VLSI Ling Adders”, in IEEE Transactions on Computers, vol. 54, no. 2, pp. 225-231, February 2005. paper

  17. G. Dimitrakopoulos and V. Paliouras, “A Novel Architecture and a Systematic Graph-Based Optimization Methodology for Modulo Multiplication”, in IEEE Transactions on Circuits and Systems I, vol. 51, no. 2, pp. 354 - 370, February 2004. paper

Conferences

  1. I. Seitanidis, G. Dimitrakopoulos, P. Mattheakis, L. Masse-Navette, D. Chinnery, "Timing Driven Incremental Multi-Bit Register Composition Using a Placement Aware ILP formulation", in Proc. ACM/IEEE Design Automation Conference (DAC), USA, June 2017. paper

  2. M. Debnath, D. Konstatinou, C. Nicopoulos, G. Dimitrakopoulos, W-M Lin, and J. Lee "Low-Cost Congestion Management in Networks-on-Chip Using Edge and In-Network Traffic Throttling" in 2nd Int'l Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems (HIPEAC-AISTECS), Sweden, 2017. paper

  3. A. Psarras, S. Moisidis, C. Nicopoulos and G. Dimitrakopoulos "RapidLink: a Network-on-Chip Architecture with Double-Data-Rate Links" , in IEEE Int'l Conference on Electronics, Circuits, and Systems (ICECS), France, Dec. 2016. paper

  4. I. Seitanidis, C. Nicopoulos and G. Dimitrakopoulos "PowerMax: An Automated Methodology for Generating Peak-Power Traffic in Networks-on-Chip" in 10th IEEE/ACM International Symposium on Networks-on-Chip (NoCS), Sept. 2016, Japan. paper Best Paper Award Finalist

  5. A. Psarras, J. Lee, P. Mattheakis, C. Nicopoulos and G. Dimitrakopoulos "A Low-Power Network-on-Chip Architecture for Tile-based Chip Multi-Processors" in ACM Great Lakes Symposium on VLSI (GLSVLSI) 2016, Boston, USA, May 2016. paper

  6. M. Paschou, A. Psarras, C. Nicopoulos and G. Dimitrakopoulos "CrossOver: Clock Domain Crossing under Virtual-Channel Flow Control" in Design Automation and Test in Europe (DATE), Dresden, Germany, Mar. 2016. paper

  7. A. Panteloukas, A. Psarras, C. Nicopoulos and G. Dimitrakopoulos "Timing Resilient Network-on-Chip Architectures" in IEEE International On-Line Testing Symposium (IOLTS), July 2015. paper

  8. A. Psarras, I. Seitanidis, C. Nicopoulos and G. Dimitrakopoulos "PhaseNoC: TDM Scheduling at the Virtual-Channel Level for Efficient Network Traffic Isolation" in Design Automation and Test in Europe (DATE), Grenoble, France, Mar. 2015. paper Best Paper Award

  9. I. Seitanidis, A. Psarras, E. Kalligeros, C. Nicopoulos, G. Dimitrakopoulos "ElastiNoC: A Self-Testable Distributed VC-based Network-on-Chip Architecture" in 8th IEEE/ACM International Symposium on Networks-on-Chip (NoCS), Sept. 2014, Italy. paper

  10. I. Seitanidis, A. Psarras, G. Dimitrakopoulos, C. Nicopoulos "ElastiStore: An Elastic Buffer Architecture for Network-on-Chip Routers", in Design Automation and Test in Europe (DATE), Mar. 2014. paper

  11. G. Dimitrakopoulos, I. Seitanidis, A. Psarras, K. Tsiouris, P. Matthaiakis, J. Cortadella "Hardware Primitives for the Synthesis of Multithreaded Elastic Systems", in Design Automation and Test in Europe (DATE), Mar. 2014. paper

  12. G. Dimitrakopoulos, N. Georgiadis, C. Nicopoulos, E. Kalligeros, "Switch Folding: Network-on-Chip Routers with Time-Multiplexed Output Ports", in Design Automation and Test in Europe (DATE), Mar. 2013. paper

  13. A. Roca, J. Flich, G. Dimitrakopoulos “DESA: Distibuted Elastic Switch Architecture for efficient Networks-on-FPGAs”, in the International Conference on Field-Programmable Logic and Applications (FPL 2012) Oslo, Norway, August 2012. paper

  14. G. Dimitrakopoulos, E. Kalligeros, “Dynamic-Priority Arbiter and Multiplexer Soft Macros for On-Chip Networks Switches”, in ACM Design Automation and Test in Europe (DATE), Mar. 2012. paper

  15. G. Dimitrakopoulos, E. Kalligeros, “Low-cost fault-tolerant switch allocator for network-on-chip routers”, Proc. of the 6th Interconnection Network Architecture, On-Chip Multi-Chip Workshop (INA-OCMC), Jan. 2012. paper

  16. G. Dimitrakopoulos, C. Kachris, E. Kalligeros, “Scalable arbiters and multiplexers for on-FPGA interconnection networks”, in Proceedings of the 21st International Conference on Field-Programmable Logic and Applications (FPL 2011) Chania, Greece, September 2011. paper

  17. G. Dimitrakopoulos and K. Galanopoulos, “Switch allocator for bufferless network-on-chip routers”, in Proceedings of the Fifth ACM Interconnection Network Architecture, On-Chip Multi-Chip Workshop (INA-OCMC) Heraklion, Greece, January 2011 paper

  18. G. Dimitrakopoulos, N. Chrysos, K. Galanopoulos “Fast Arbiters for On-Chip Network Switches”, in IEEE International Conference on Computer Design (ICCD), Oct. 2008. paper

  19. N. Chrysos and G. Dimitrakopoulos “Backlog-Aware Crossbar Schedulers: A New Algorithm and its Efficient Hardware Implementation”, in IEEE Symposium on High-Performance Interconnects (HOT-Interconnects), pp. 67-74, Aug. 2008. paper

  20. G. Dimitrakopoulos, C. Mavrokefalidis, K. Galanopoulos, and D. Nikolos, “An Energy-Delay Efficient Subword Permutation Unit”, in IEEE Conference on Application Specific Systems, Architectures, and Processors (ASAP), Sept. 2006. paper

  21. G. Dimitrakopoulos, C. Mavrokefalidis, K. Galanopoulos, and D. Nikolos, “Fast Bit Permutation Unit for Media-Enhanced Microprocessor”, in IEEE International Symposium on Circuits and Systems (ISCAS), May 2006. paper

  22. G. Dimitrakopoulos, D. G. Nikolos, H. T. Vergos, D. Nikolos, and C. Efstathiou, “New architectures for modulo 2n-1 adders”, in IEEE International Conference on Electronics, Circuits and Systems (ICECS), December 2005. paper

  23. G. Dimitrakopoulos and D. Nikolos, “Closed-Form Bounds for Interconnect-Aware Minimum Delay Gate Sizing”, in International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2005), Lectures Notes in Computer Science, vol. 3728, pp. 308 - 317, Sep. 2005 paper

  24. G. Dimitrakopoulos, P. Kolovos, P. Kalogerakis, and D. Nikolos, “Design of High-Speed Low-Power VLSI Parallel-Prefix Adders”, in Proceedings of the 14th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2004), Lectures Notes in Computer Science, vol. 3254, pp. 248 - 257, August 2004. paper

  25. C. Efstathiou, H. Vergos, G. Dimitrakopoulos, and D. Nikolos, “Efficient Modulo 2n + 1 Tree Multipliers for Diminished-1 Operands”, in Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems (ICECS’ 03), December 2003, pp. 200-203. paper

  26. G. Dimitrakopoulos, H. T. Vergos, D. Nikolos, and C. Efstathiou, "A Family of Parallel Prefix Modulo 2n-1 Adders’, in Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP’03), June 2003, pp. 326 - 336. paper

  27. G. Dimitrakopoulos, X. Kavousianos, and D. Nikolos, “Virtual-Scan: A Novel Approach for Software-Based Self-Testing of Microprocessors”, in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS’03), May 2003, pp. 237-240. paper

  28. G. Dimitrakopoulos, H. T. Vergos, D. Nikolos, and C. Efstathiou, “A Systematic Methodology for Designing Area-Time Efficient Parallel-Prefix Modulo 2n - 1 Adders”, in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS’ 03), May 2003, pp. 225-228. paper

  29. G. Dimitrakopoulos, X. Kavousianos, and D. Nikolos, "Software-Based Self-testing of Microprocessors by Exploiting a Virtual Scan Path’, in the Supplement of the 4th European Dependable Computing Conference (EDCC-4), October 2002, pp. 23-24. paper

  30. G. Dimitrakopoulos and V. Paliouras, “Graph-Based Optimization for a CSD-Enhanced RNS Multiplier”, in Proceedings of the 45th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS’02), August 2002, Volume III, pp. 648-651 paper

  31. G. Dimitrakopoulos, D. Nikolos, and D. Bakalis, “Bit-Serial Test Pattern Generation by an Accumulator Behaving as a Non-Linear Feedback Shift Register”, in Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW’02), July 2002, pp. 152-157. paper

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