The papers and their abstracts, which represent the so far published work of the author, are given below. If you have any question, please, contact the author.






Quaternary voltage-mode CMOS circuits for  multiple-valued logic

Design of novel multiple-valued logic voltage-mode storage circuits

    Novel multiple-valued logic (MVL) voltage-mode storage circuits, namely the dynamic and pseudo-static latch, and the dynamic and pseudo-static master-slave, using enhancement- or both enhancement- and depletion-mode MOSFETs, are proposed. These storage circuits consist of some new building units. Low power dissipation, zero static power consumption during the steady state operation and high speed characterize the proposed circuits. Additionally, we extend the use of fundamental principles of the True Single-Phase Clocked Logic approach of binary logic to MVL, which implies smaller switching activity. Considering quaternary logic, the proposed circuits are simulated by SPICE tool. The obtained result proclaims substantial improvements, in terms of power, speed, and transistor count. Adopting the principal design concepts of the proposed quaternary circuits, we developed a generalized formal methodology for systematic design of storage circuits of any radix. Both the methodology and the proposed circuits exhibit regular, modular, iterative and hierarchical designed architectures, which eventually imply regular physical implementations suitable for VLSI implementations. Back to Journals

Quaternary voltage-mode multiple-valued logic adder circuits

    Abstract is not yet available. Back to Journals

A unified environment for digital systems simulation

    Here is presented a Unified Environment for the simulation of digital systems. This Environment was designed originally for a Macintosh computer. Its main features are (a) the introduction of a third (unknown) logical state, (b) a fast simulation algorithm, (c) ability to run on small computers and (d) is designed on the principles of Open Systems. Back to Conferences

Multiple-valued logic voltage-mode storage circuits based on true-single-phase clocked logic

Design methodology of multiple-valued logic voltage-mode storage circuits

The design of low power multiple-valued logic encoder and decoder circuits

    Novel multiple-valued logic (MVL) voltage-mode circuits, namely encoder and decoder circuits, using both enhancement- and depletion-mode MOSFETs, are introduced. High performance and low power dissipation, due to zero-static power consumption during their steady-state operation, characterize the proposed circuits. More specifically, considering quaternary logic, and 0.7 um technology, the encoder and decoder circuits are implemented and simulated by the SPICE tool. The results obtained show substantial improvements, in terms of power, speed, and transistor count, compared with existing designs. Back to Conferences

The circuit design of multiple-valued logic voltage-mode adders

    Novel quaternary half adder, full adder, and a carry-lookahead adder are introduced. The proposed circuits are static and operate in voltage-mode. Moreover, there is no current flow in steady states, and thus, no static power dissipation. Although the comparison in transistor count shows that the proposed quaternary circuits are larger than two respective binary ones, benefits in parallel addition arise from the use of multiple-valued logic. Firstly, the ripple-carry additions are faster because the number of carries are half compared to binary ones and the delay from the input carry through the output carry is relatively small. Secondly, the carry-lookahead scheme exhibits less complexity, which leads to overall reduction in transistor count for addition with large number of bits. Back to Conferences

Back to Home Page

VLSI Design and Testing Center Home Page   Laboratory of Electrical and Electronic Materials Technology Home Page