Book Cover

Microarchitecture of Network on Chip Routers: A Designer's Perspective

Giorgos Dimitrakopoulos, Anastasios Psarras, Ioannis Seitanidis
Springer, Oct 2014
ISBN: 978-1-4614-4300-1


The Network-on-chip paradigm solves the problem of efficient on-chip communication by applying at the silicon chip level well established networking principles, after suitably adapting them to the silicon chip characteristics and to application demands. The routers are the heart and the backbone of the network-on-chip and their purpose is to provide arbitrary connectivity between inputs and outputs and allow for the implementation of arbitrary network topologies. This book focuses on the microarchitecture of network-on-chip routers following a designer's perspective and providing ready-to-use solutions for simple or more sophisticated design cases. All aspects of the design of a network-on-chip router, including flow control, buffering architectures, arbitration and allocation, as well as pipelined organizations, are presented in detail building on top of detailed examples and practical abstract models, when necessary. Router micro-architectural options are presented in a step-by-step manner beginning from the basic design principles. Even highly sophisticated design alternatives are categorized and broken down to simpler pieces that can be understood easily and analyzed. This book is an invaluable reference for system, architecture, circuit, and EDA researchers and developers, who are interested in understanding the overall picture of network-on-chip routers' microarchitecture, the associated design challenges, and the available solutions.

Preface & Table of Contents [PDF]

Resources - Powerpoint slides (available soon)

  • Chapter 1: Introduction to Network-on-Chip Design
  • Chapter 2: Link-level flow control and buffering
  • Chapter 3: Baseline switching modules and routers
  • Chapter 4: Arbitration logic
  • Chapter 5: Pipelined wormhole routers
  • Chapter 6: Virtual-channel flow control and buffering
  • Chapter 7: Baseline virtual-channel based switching modules and routers
  • Chapter 8: High-speed allocators for VC-based routers
  • Chapter 9: Pipelined virtual-channel-based routers